Eight-Tap Adaptive Equalizer for Partial-Response Channels
نویسنده
چکیده
A new architecture for digital implementation of the adaptive equalizer in Class IV partial-response maximum likelihood (PRML) channels employing parallelism and pipelining is described. The architecture was used in a prototype integrated circuit in a 1.2 pm CMOS technology to implement an eight-tap adaptive equalizer and Viterbi sequence detector which consumes a total of 70 mW from a 3.3 V supply operating at an input sampling rate of 50 MHz.
منابع مشابه
A 50 MHz 70 mW & Tap Adaptive EqualizerlViterbi Sequence Detector in 1 . 2 pm CMOS
A new architecture for digital implementation of the adaptive equalizer in Class IV Partial Response Maximum Likelihood (PRML) channels employing parallelism and pipelining is described. The architecture was used in a prototype integrated circuit in a 1.2 pm CMOS technology to implement a 50 MHz adaptive equalizer and Viterbi sequence detector dissipating 70 mW from a 3.3 V supply. 1 .O Introdu...
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